SPE Signal Integrity Engineer

SPE Signal Integrity Engineer

 In this highly visible role, you will work within our SI/PI team to work on modelling, analysis, and simulations of Signal Integrity and Power Integrity in the very challenging DDR field with speed up to 12800+ MT/s. Reporting directly to the VP of Engineering
 

Responsibilities:

• Create SI/PI methodologies and work with the Design and SI teams to do SI/PI study and package design for the latest DDR product portfolio
• Work with our design team and validation team to define specifications and system design requirements such as packaging and PCB routings, IC-PKG-BRD decoupling requirements, channel simulations and jitter sensitivity analysis
• Provide guideline to design team based on SI/PI study and simulation and silicon correlation so that our products will have superior SI performance, i.e. best RMT scores
• Work with our customers to do collaboration to find the optimum SI/PI solution
• Help the team during debug and bring up in lab if needed

 
Qualifications:

• Solid background in SI/PI and package design to provide technical leadership to the team
• Strong interpersonal skill to keep the team motivated and focused
• MS or PhD in Electrical Engineering with 10+ years of industry experience in which at least a few years with exposure to DDR4/5
• Prior experience in simulating high speed memory (DDR4, DDR5) and/or SERDES interfaces is required
• Solid theoretical background and understanding in EM and transmission line theory is a must
• Strong background and solid understanding of equalization techniques such as FIR/FFE/DFE/CTLE are required
• Must understand package and PCB design, be able to edit APD/Allegro layout files. Know SI/PI driven BGA assignment methodology and be able to simulate for the trade-offs in the context of a system
• Extensive experience in correlating simulation results with lab measurements using scopes, TDRs, VNAs etc.
• Strong understanding of the server system, from CPUs to DRAMs on DIMM modules, is highly desirable
• Know the mechanisms of crosstalk and jitter in source-synchronous interfaces and be able to include the effect of such losses into low BER simulations
• Proficient with simulations using Spice and ADS
• Experience with commercial EDA tools such as ADS, HFSS, Q3D/PowerSI
• Familiarity with RedHawk/Totem or XcitePI and Virtuoso is a strong plus
• Lab characterization experience of passive components, link margin, or noise using real time/sampling scopes and VNA/TDR is a big plus
• Basic knowledge of circuits used in high-speed link design is preferred.
• Excellent writing and presentation skills are essential as well as good communication skills to work with customers and cross-functional teams.
• Must be an innovative, self-motivated individual, be able to manage and drive his projects, and must be a team player