Senior Digital Verification Engineer

Senior Digital Verification Engineer

Position Overview

A global leader in high-speed networking and communications technologies is seeking a Senior Digital Verification Engineer to contribute to the verification and validation of advanced digital communication and signal processing systems.

This role focuses on defining and implementing robust verification strategies for complex digital subsystems used in high-performance connectivity platforms. The successful candidate will work closely with architects, digital designers, and systems engineers to ensure comprehensive functional validation across sophisticated hardware designs.

Key Responsibilities

Verification Strategy & Planning

• Analyze architecture and functional specification documents to define verification requirements.
• Develop comprehensive:
  • Verification plans
  • Functional coverage plans
  • Formal verification strategies
• Propose innovative verification methodologies for complex digital subsystems.

Testbench Development & Validation

• Design and implement verification environments using:
  • SystemVerilog
  • UVM methodologies
  • Assertion-based verification techniques
• Develop:
  • Testbench components
  • Verification agents
  • Scoreboards
  • Directed and constrained-random test scenarios
• Support both simulation-driven and formal verification workflows.

Coverage-Driven Verification

• Execute coverage-driven verification methodologies.
• Monitor regression environments and analyze failures.
• Collaborate with design engineers to debug and resolve issues efficiently.
• Ensure complete validation of assigned architectural blocks.

Cross-Functional Collaboration

• Work closely with:
  • System architects
  • Digital design teams
  • Verification engineers
• Participate in technical discussions and status reporting.
• Contribute to overall verification methodology improvements.

Required Qualifications

• Bachelor’s or Master’s degree in:
  • Electrical Engineering
  • Computer Engineering
  • Computer Science
  • Related technical field
• Strong expertise in:
  • SystemVerilog
  • SystemVerilog Assertions (SVA)
  • Digital simulation tools
• Proven ability to define comprehensive verification and coverage strategies.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills in English.
• Ability to work independently while contributing effectively within teams.

Preferred Qualifications

• Experience with:
  • UVM verification methodologies
  • Formal verification techniques
  • DSP or forward error correction systems
  • Mixed-signal validation
• Familiarity with communication standards and protocols such as:
  • Optical transport protocols
  • High-speed Ethernet
  • Broadband communication standards
• Experience using:
  • Git or similar version control systems
  • Bug tracking and workflow tools
• Knowledge of additional programming or scripting languages including:
  • Python
  • C/C++
  • Bash
  • SystemC
  • Make