VP of Engineering

Our Semiconductor/Deep-Tech client is building an agentic AI platform for digital verification, designed to help semiconductor teams accelerate verification planning, execution, debugging, root-cause analysis, and closure.
Their platform combines AI agents, RAG-based design collateral ingestion, verification workflow automation, and logic-aware analysis to support complex digital verification environments.
They are looking for a US-based senior verification leader who can bridge customer needs, product direction, and engineering execution.

Role Overview
They are seeking a VP of Engineering who combines deep digital verification expertise, strong familiarity with EDA verification tools, software product engineering leadership, and practical experience applying AI to complex engineering workflows. This person should be able to engage credibly with customers, translate their needs into technical direction, and lead engineering teams toward production-grade execution.
This is a full-time strategic and technical leadership role. You will work directly with semiconductor customers to understand their verification workflows, define product requirements, shape high-value use cases, support pilots, and translate real customer needs into clear engineering priorities. At the same time, you will lead and mentor cross-functional engineering teams, ensuring customer requirements are transformed into a scalable, production-grade, world-class AI verification platform.
The ideal candidate has strong experience in coverage-driven verification, formal verification, emulation, verification IP, debug, regression analysis, coverage closure, and verification planning, and can confidently interface with both semiconductor customers and internal product/engineering teams.

What You’ll Lead
You will own the technical customer-facing function for their original AI agentic verification platform.
You will:

• Lead technical discovery with semiconductor customers to understand verification workflows, pain points, requirements, adoption concerns, and success criteria.
• Translate customer requirements into clear product use cases, workflow definitions, technical specifications, and roadmap priorities.
• Lead engineering execution, architecture, delivery quality, and technical roadmap implementation, and act as the bridge between customers, product strategy, and engineering execution.
• Define how the platform fits into real verification environments, including simulation, formal, emulation, regressions, debug, CI/CD, coverage, and existing EDA toolchains.
• Support customer demos, proof-of-concept engagements, pilot planning, and technical evaluations.
• Mentor internal engineering teams on verification methodology, user expectations, EDA workflows, and practical customer requirements.
• Review product workflows, demos, and technical outputs to ensure they are credible, useful, and aligned with how verification teams actually work.
• Help define proof-of-value metrics that matter to verification leaders, such as debug time reduction, faster root-cause analysis, improved planning quality, better regression insight, or reduced manual effort.
• Support strategic introductions and customer-facing conversations across the US semiconductor ecosystem.
• Help refine against existing EDA tools, internal automation flows, and general-purpose AI assistants.

 
What They’re Looking For
They are looking for someone with:

• BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience across semiconductor, EDA, and digital verification environments, with deep expertise in verification workflows, methodologies, and tools across IP, subsystem, and SoC-level projects.
• Experience working directly with semiconductor customers, verification teams, EDA users, or internal engineering stakeholders.
• Ability to convert complex technical discussions into structured product requirements and engineering priorities.
• Strong communication skills with both senior customer stakeholders and hands-on engineers.
• Ability to mentor engineering teams and help them understand verification workflows, customer expectations, and tool usability requirements.
• Strong product sense: the ability to identify what customers will actually use, evaluate, trust, and pay for.
• Strong US-based semiconductor ecosystem network, preferably in the Bay Area, Austin/Texas, or another major US semiconductor hub.
• Prior experience at, or working closely with, semiconductor companies, EDA companies, IP vendors, or verification tool teams.

Why Join
This is an opportunity to help define a new category at the intersection of:
AI agents × semiconductor verification × enterprise engineering automation
You will work directly with the founding team to shape the product, architecture, technical roadmap, customer strategy, and engineering culture from an early stage.